Intel processors (microarchitectural data sampling): MULTI-TENANT ISOLATION: One of the MDS family: uncacheable-memory

Impact

MULTI-TENANT ISOLATION: One of the MDS family: uncacheable-memory accesses leave sampleable residue in microarchitectural buffers. The operator-relevant consequence is that data crosses between hyperthread siblings, between VMs, and out of enclaves without any architectural access - so on a node with SMT enabled and untrusted co-tenants, tenant isolation is not holding.

Who can reach it

Local code on the same physical core - with SMT enabled that includes a co-tenant on the sibling thread, which is the configuration most density-optimised fleets run.

What to do

Mitigated by an Intel microcode update plus OS/hypervisor changes. Microcode for this class is normally shipped by your distribution as an early-loadable image, so you can deploy it with a package update and a reboot without waiting for an OEM BIOS release - that distinction is the difference between a week and a quarter. Verify after reboot by reading /sys/devices/system/cpu/vulnerabilities/ rather than assuming the package took effect. The software half is buffer clearing on context switch (VERW), already in current kernels. On nodes that host untrusted co-tenants, also disable SMT or enforce core scheduling; that costs real throughput and is a capacity-planning decision, not a free toggle.

References