AMD processors - PREFETCH instruction timing and power side channel: MULTI-TENANT ISOLATION: Timing and power

Impact

MULTI-TENANT ISOLATION: Timing and power measurements around the x86 PREFETCH instructions leak kernel address space layout on some AMD CPUs. Defeating KASLR is not itself a compromise, but it is the step that converts an unreliable kernel memory-corruption bug - and the amdgpu/amdkfd driver long tail is full of them - into a reliable exploit. Treat it as an exploitability multiplier for everything else in this database.

Who can reach it

Local, unprivileged. Reachable from inside a container.

What to do

Mitigated by AMD microcode plus, on most of these, a kernel-side change - and the durable delivery vehicle is the OEM SBIOS/AGESA package, which carries **one to six months of OEM lag** and needs a drained node and a full power cycle. The linux-firmware amd-ucode blobs get you the microcode sooner via initramfs early-load and a reboot, but AMD does not support late-loading microcode on a running EPYC host, so either way this is reboot-required, not a live patch. Kernel-side mitigation also exists. Because the value of this bug is chaining, the practical defence is to keep the kernel memory-safety patches current rather than to treat KASLR as a real boundary.

References