AMD processors - transient execution beyond unconditional direct branches: MULTI-TENANT ISOLATION: Some AMD CPUs

Impact

MULTI-TENANT ISOLATION: Some AMD CPUs transiently execute instructions past an unconditional direct branch - code that should never run, running speculatively and leaving traces in the cache. That gives an attacker speculative gadgets in places the compiler and the kernel's own Spectre auditing assume are unreachable, so hardened code can still leak. The practical outcome is data disclosure across privilege and guest boundaries.

Who can reach it

Local, from an unprivileged process or a guest VM.

What to do

Mitigated by kernel-side changes that insert INT3 speculation barriers after unconditional branches in sensitive paths. Take the distro kernel update and reboot; no firmware step for the kernel mitigation itself. Mitigated by AMD microcode plus, on most of these, a kernel-side change - and the durable delivery vehicle is the OEM SBIOS/AGESA package, which carries **one to six months of OEM lag** and needs a drained node and a full power cycle. The linux-firmware amd-ucode blobs get you the microcode sooner via initramfs early-load and a reboot, but AMD does not support late-loading microcode on a running EPYC host, so either way this is reboot-required, not a live patch.

References