AMD Secure Processor - hardware config integrity across power save/restore: MULTI-TENANT ISOLATION: Hardware

Impact

MULTI-TENANT ISOLATION: Hardware configuration state is not properly preserved across a power save/restore cycle in the ASP, so an attacker who can write outside the Trusted Memory Range can change security-relevant configuration that comes back wrong after resume. Suspend/resume is a soft spot in every confidential-computing design; here it is the ASP's own configuration that fails to survive intact.

Who can reach it

Local, requires the ability to write outside the TMR - host-privileged code - and a power-state transition to land on.

What to do

Fixed in AMD reference firmware (AGESA / SEV firmware) and delivered to you only as an OEM SBIOS/BIOS package - Dell, HPE, Supermicro, Lenovo, Gigabyte and the ODMs each rebuild and requalify AMD's AGESA drop before it ships. **Expect months, not weeks**: AMD publishes the bulletin, the OEM ships BIOS somewhere between one and six months later, and for platforms past their support window it may never arrive at all. Applying it is a full node power cycle with the host drained - not a driver reload, not a live patch. Track it as a firmware campaign per server SKU, not per kernel version, and verify afterwards by reading back the SMU/PSP firmware version rather than trusting the BIOS revision string. Because this sits inside the SEV-SNP trust boundary, the update also moves the platform's reported TCB version: after patching you must refresh VCEK certificates from AMD's KDS and update whatever attestation policy your tenants (or your own confidential-VM control plane) pin against, or every guest launch will start failing validation. Servers rarely suspend, so on a datacenter fleet the practical exposure is lower than the score suggests; still worth catching in the next BIOS wave.

References