AMD processors - speculative inference of control registers despite UMIP: MULTI-TENANT ISOLATION: Part of the Transient

Impact

MULTI-TENANT ISOLATION: Part of the Transient Scheduler Attacks batch AMD disclosed in July 2025. A user process can speculatively infer the contents of control registers even when UMIP - the feature specifically added to stop userspace reading them - is enabled. Control register contents leak kernel configuration and address-layout information, which is the reconnaissance step that makes a subsequent kernel exploit reliable. Low score, real utility to an attacker chaining it.

Who can reach it

Local, unprivileged user process. Part of the TSA family that also covers cross-thread and cross-privilege leakage on affected Zen parts.

What to do

Mitigated by AMD microcode plus, on most of these, a kernel-side change - and the durable delivery vehicle is the OEM SBIOS/AGESA package, which carries **one to six months of OEM lag** and needs a drained node and a full power cycle. The linux-firmware amd-ucode blobs get you the microcode sooner via initramfs early-load and a reboot, but AMD does not support late-loading microcode on a running EPYC host, so either way this is reboot-required, not a live patch. AMD shipped the TSA mitigations in microcode plus a kernel change (VERW-based clearing on transitions) in the July 2025 wave. Patch the whole TSA batch together - the siblings covering store-queue and L1 leakage carry the higher scores. Some TSA mitigations cost measurable performance on context-switch-heavy workloads, so benchmark before you assume the fix is free.

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