Arm C1-Pro before r1p2; Trusted Firmware-A v2.10 and later on multi-core configurations with the CME complex enabled

Impact

SME / SVE / SIMD memory accesses on one core can outlive another core's TLB invalidate and barrier, so vector loads and stores complete against a translation that was supposed to be dead. The consequence is memory touched outside the expected translation or privilege boundary. Because SME and SVE are exactly what ML kernels use, this is a fault that fires most readily under the workload you actually run, not under a synthetic test.

Who can reach it

Requires code on multiple cores of an affected C1-Pro part - a guest or host process issuing wide vector memory operations while another core performs TLB maintenance. Local only.

What to do

The TF-A mitigation is heavy: EL3 coordinates a secure-SGI rendezvous across cores using atomic counters, and the OS must call into that SMC interface during affected TLB maintenance. So you need both an OEM firmware build with WORKAROUND_CVE_2026_0995=1 and a patched kernel; neither alone is sufficient. Flash + reboot + drain, plus a kernel roll. Silicon revision r1p2 and later does not need it, so on a fleet refresh this is a spec item to demand from the vendor rather than a patch to carry forever.

References